Integrating the Power Ring: Modifying an Existing Design

Fig. 1: Typical planer inverter layout
The “stacked” inverter design evolves from modifying a typical automotive inverter by utilizing the excess space left above the IGBT module (see figure 1). By bending the end of co-planar bus plate (see figure 2), the IBGT, die, cooling plate, and the ring capacitor are “stacked” on top of each other in a symmetrical fashion. The ring capacitor is placed underneath the cooling plate. The cooling plate is shared with the IGBT module which is mounted on the top. Figure 10 shows the “stacked’ inverter design after the integration of the ring capacitor and the co-planar bus plate. It should also be noted that in some design examples, the “stack” is inverted with the capacitor is on the top of the stack and the IGBT modules are on the bottom. The resulting advantages are the same in either configuration. It is the designer’s choice which one is on the top vs. the bottom.

Fig. 2: Annular Capacitor with vertical enabling bus plate- “cap on bottom” implementation

Depending on the dimensions and specifications of the existing design, a “stacked” design can deliver up to 30% volume reduction and W/cm3 based solely on the vertical integration process. With these improvements come weight reductions and cost reductions due do less film, potentially less bus materials, less packaging materials and the possible elimination of snubbers depending on choices made.
The final total inductance of the stacked vertical design has to be carefully considered when choices are being made. If care is not taken as to how long the “loop” portion of the folded over bus is, the resulting inductance could become unacceptably high.
Of course, if you look at figure 3, you will see that the width of the required cooling plate for both the capacitor and the IGBT modules is directly proportional to the length of the bend in this configuration.

Fig. 3: Stacked Vertical IGBT – Cap arrangement

There is also the ability to integrate the low ESR characteristics of the annular shape into the final design for further reduction of volume of the capacitor itself for a given power density or to minimize cooling needs, and thereby reducing overall bus inductance. By now combining both aspects of vertical integration and the low temperature rise characteristics of the capacitors, an increase to 50% or more volume reduction is realistically possible (spatial reduction and capacitor volume size reduction). And by using the simulation tools now available and validated, such achievements can be done without sacrifice of system reliability.
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